Responsibilities: As Digital Design Engineer, • Responsible for RTL design and verification using Verilog and System Verilog • Define System Architecture and/or Block level Micro Architecture based on product features and performance requirements, also with gate
Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the
Appealing Points: Design and verify advanced semiconductor digital circuits using Verilog-HDL and SystemVerilog, including assertions, waveform analysis, and coverage verification. Work across the chip development lifecycle, from circuit specification and RTL design to power analysis, synthesis, physical