Req. ID: 291683 

The R&D ESD/Latch-up Design and Characterization team in TD at Micron Technology, Inc. is seeking an experienced ESD Engineer with emphasis conducting ESD/LUP research and experiments to investigate how to design-in the best ESD and latch-up circuit solutions for memory designs.

 Successful candidates for this position will have:

• A strong experience of advanced semiconductor device physics, including deep submicron CMOS devices.

• A good understanding of state-of-the-art CMOS process technology and electrical circuit analysis.

• A solid knowledge of ESD circuit design and how they are applied to provide protection in advanced CMOS technologies.

• Experience in Cadence design tools for design, layout and verification.

• Hands on experience in ESD/Latch-up characterization tests using wafer level transmission line pulse (TLP) test equipment and semiconductor parametric analyzer, current and voltage meters.

• Experience in waveform generators, oscilloscopes, source/measure units, Agilent and/or Keithley parametric analyzers/testers, and impedance analyzers.

• Familiarity with ESD analysis tools like PERC or PathFinder or similar software tools.

• Strong data analysis skills are required to extract the high current ESD properties and develops ESD/Latch-up design rules for critical ESD circuits.

• Strong oral and written English communication skills is desired to provide ESD/LUP technical leadership with diverse worldwide teams in Design, Product Engineering, R&D characterization, and Quality Assurance.


An MS/PhD in Electrical Engineering, Microelectronics, or related discipline.  BS + minimum of 5 years of relevant experience will also be considered. An ESD Certified Professional Design Certification from the ESD Association would be strongly desired.


Kanagawa, Japan

We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law.  This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.

Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.

To request assistance with the application process, please contact Micron’s Human Resources Department at 1-800-336-8918 (or 208-368-4748).

Keywords:  Hashimoto || Kanagawa (JP-14) || Japan (JP) || Technology Development || Experienced || Regular || Engineering || #LI-MO1 ||

R&D ESD Design Engineer

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