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Responsibilities: As Digital Design Engineer, • Responsible for RTL design and verification using Verilog and System Verilog • Define System Architecture and/or Block level Micro Architecture based on product features and performance requirements, also with gate count and power estimation
The candidate required to work at Tokyo, Japan. Client Overview Our client is a leading global IT services and digital transformation enterprise operating at the forefront of enterprise computing, cloud-native infrastructure, artificial intelligence, and advanced software engineering.
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