Responsibilities: Responsible for RTL design and verification using Verilog and System Verilog Define System Architecture and/or Block level Micro Architecture based on product features and performance requirements, also with gate count and power estimation Work closely
Responsibilities: As an Application engineer for CIS, you will be responsible to: Conduct analytic studies of fundamental performance issues for CIS or ISP and provide technical suggestions of improvement Support customer and solve their issue with
• Define System Architecture of array readout circuit based on product features and performance requirements. • Work closely with digital, layout, process, evaluation engineers to debug, optimize performance of image sensors and successfully bring new products
Responsibilities: Develop advanced CIS technologies and lead project through detailed process and process integration knowledge. Complete the project from NTO to risk mass production phase to meet all PRD targets and enough yield/qualification evidence. Work with pixel