Job Description Position Overview The Layout Tape-Out Support Engineer is responsible for end-to-end tape-out execution for Gallium Nitride (GaN) technologies. This role supports multiple concurrent tape-out flows, ensuring accurate, high-quality mask data delivery while enabling effective
Job Description • Lead semiconductor package design in collaboration with IC design engineers to optimize product cost and performance. • Lead the layout design of package substrates and printed circuit boards for reference designs for semiconductor products incorporating
Job Description We are seeking GaN Device Staff Engineer to drive next-generation high-efficiency power conversion technologies for emerging applications. In this role, you will participate throughout the full technology and product development cycle, from device concept
Job Description Job Description You will develop technologies and systems to fundamentally improve the efficiency of test development and characterization processes for automotive MCU/SoC products. Your role spans both technical workflow design and system automation, enabling
Job Description 1. Facilitate process change review via physical meeting or system. 2. Coordination with cross functional team to achieve internal approval as well as customer approval. 3. KPI tracking in periodic basis. Qualifications 【Must-have】 1.
Job Description • Technical Domain Layout design for non-volatile memory (NVM) IP, including Flash, MRAM, and ReRAM • Target Products MCUs for automotive, industrial, and IoT applications • Project Overview Layout design for NVM IP based
Job Description Responsibilities Single point of contact on functional safety for lead customers and their certification bodies; present and defend the safety concept, safety manual and FMEDA. Derive the IC-level safety requirements with customer system safety
Job Description Lead the development of CPU Subsystems (CPUSS), a core component of next-generation microcontrollers. Drive the architecture definition, specification development, design, and verification of CPU subsystem components, including CPU cores, caches, memory protection mechanisms, debug
Job Description You will play a key role in strengthening the security of Renesas Embedded Processing (EP) products, including MCUs, MPUs, wireless connectivity devices, AI accelerators, and system solutions. As a member of the EP Core
Job Description 当社は2035年までに収益200億ドル超の達成を目標に掲げ、先端半導体ソリューションの可能性をさらに広げてまいります。技術革新が加速する今こそ、その最前線で共に挑戦できる環境をご用意しております。 この挑戦を共に牽引していただけるエンジニアを探しております。我々のチームでは、互いの専門性を尊重し高め合いながら成長できる風土を大切にしております。これまでの経験とスキルを活かし、共に新たな価値を創造していただける方をお待ちしております。 (English) Our company aims to surpass $20 billion in revenue by 2035, further expanding the potential of advanced semiconductor solutions. As technological innovation accelerates, we offer an environment where you can take on
求人内容 【Background】 Renesas is strengthening its EDA (Electronic Design Automation) infrastructure operating model in Japan. We are looking for an EDA Infrastructure Engineer to support and improve Linux-based servers, storage systems, and related infrastructure that enable
Job Description • Technical Domain Layout design for non-volatile memory (NVM) IP, including Flash, MRAM, and ReRAM • Target Products MCUs for automotive, industrial, and IoT applications • Project Overview Layout design for NVM IP based