安定的な生産を継続するために検査および包装ラインのメンテナンスおよびエンジニアリングを行う。 Responsible for the maintenance and engineering of inspection and packaging line to continue the operation with good condition. • GMP/GCTP • Japanese laws and regulations •メンテナンスエンジニアは富士工場の生産設備を維持し,円滑な生産をサポートする。(トラブルシューティングを含む) Maintenance engineer is keeping the Fuji-site equipments, supporting to stable
Position Summary : Lead Engineering and C&Q (Commissioning and Qualification) Team at Fuji Site in alignment with/and implementing global guidelines , in following areas: - Engineering and Project Management, - Commissioning and Qualification plan and execution, guaranteeing a
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Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
A Full Chip PnR (Place and Route) Lead is a senior-level position in semiconductor companies responsible for leading the physical design implementation process, including place and route, for entire chip designs. The job description for this
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A Physical Design Engineer with 4-8 years of experience plays a crucial role in semiconductor companies, focusing on the implementation of integrated circuit (IC) designs into physical layouts suitable for fabrication. The job description for this
A SoC Pre-Sil Verification Engineer with 9 to 15 years of experience is a senior-level position in semiconductor companies involved in the pre-silicon verification of System-on-Chip (SoC) designs. The job description for this role typically includes
