Responsibilities: Responsible for RTL design and verification using Verilog and System Verilog Define System Architecture and/or Block level Micro Architecture based on product features and performance requirements, also with gate count and power estimation Work closely
Job responsibilities: • Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) • Define ISP HW Architecture based on product features and performance requirements, also with gate count and power
Responsibilities: As an Application engineer for CIS, you will be responsible to: Conduct analytic studies of fundamental performance issues for CIS or ISP and provide technical suggestions of improvement Support customer and solve their issue with
Responsibilities: The imaging algorithm engineer will apply knowledge of image sensor and camera system to, scientifically, analyze key performance of OmniVision’s products and provide technical suggestions of improvement. Conduct analytic studies of fundamental performance issues for