Responsibilities: As Digital Design Engineer, • Responsible for RTL design and verification using Verilog and System Verilog • Define System Architecture and/or Block level Micro Architecture based on product features and performance requirements, also with gate count
About the job Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam DAngelo, Larry Summers, and Jack Dorsey. Position: Application
Appealing Points: Design and verify advanced semiconductor digital circuits using Verilog-HDL and SystemVerilog, including assertions, waveform analysis, and coverage verification. Work across the chip development lifecycle, from circuit specification and RTL design to power analysis, synthesis, physical
About the job Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam DAngelo, Larry Summers, and Jack Dorsey. Position: Application
About the job Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam DAngelo, Larry Summers, and Jack Dorsey. Position: Software
About the job Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam DAngelo, Larry Summers, and Jack Dorsey. Position: Software